1. Field of the Invention Display
The present invention relates to a display and more particularly, it relates to a display provided with a shift register circuit.
2. Description of the Background Art
Conventionally, a resistance loading type of inverter circuit has been well known. This is disclosed in p.184-187 in “Basis of Semiconductor Devices” written by Seigo Kishino, published by Ohmsha, Ltd., Apr. 25 in 1985, for example. In addition, conventionally, a shift register circuit comprising the above-described resistance loading type of inverter circuit has been known. The shift register circuit is used as a circuit for driving a gate line or a drain line of a liquid crystal display or an organic EL display, for example.
FIG. 17 is a circuit diagram showing a shift register circuit comprising the conventional resistance loading type of inverter circuit. Referring to FIG. 17, a conventional shift register circuit 100a consists of a first circuit part 101a and a second circuit part 102a. A second stage of shift register circuit 100b consists of a first circuit part 101b and a second circuit part 102b. 
The first circuit part 101a constituting the first stage of shift register circuit 100a comprises n-channel transistors NT101 and NT102, a capacitor C101, and a resistance R101. Hereinafter, the n-channel transistors NT101 and NT102 are referred to as the transistors NT101 and NT102, respectively in the description of the prior art. A source of the transistor NT101 is connected to a node ND101 and a start signal ST is input to a drain thereof. A clock signal CLK1 is supplied to a gate of the transistor NT101. In addition, a source of the transistor NT102 is connected to a negative-side potential VSS and a drain thereof is connected to anode ND102. In addition, one electrode of a capacitor C101 is connected to the node ND101 and the other electrode is connected to the negative-side potential VSS. In addition, one terminal of a resistance R101 is connected to a positive-side potential VDD and the other terminal is connected to the node ND102. Thus, the transistor NT102 and the resistance R101 constitute an inverter circuit.
In addition, a second circuit part 102a constituting the first stage of shift register circuit 100a comprises an n-channel transistor NT103 and a resistance R102. Hereinafter, the n-channel transistor NT103 is referred to as a transistor NT103 in the description of the prior art. A source of the transistor NT103 is connected to the negative-side potential VSS and a drain thereof is connected to a node ND103. One terminal of the resistance R102 is connected to the positive-side potential VDD and the other terminal is connected to the node ND103. Thus, the transistor NT103 and the resistance R102 constitute an inverter circuit.
In addition, the second or later stage of shift register circuit also has the same circuit constitution as that of the above-described first stage of shift register circuit 100a. In addition, it is constituted such that the first circuit part of the latter stage of shift register circuit is connected to the output node of the former stage of shift register circuit. In addition, the clock signal CLK1 is supplied to the gate of the transistor NT101 of the first circuit part arranged at the odd-numbered stage as described above, and a clock signal CLK2 is supplied to the gate of the transistor NT101 of the first circuit part arranged at the even-numbered stage.
FIG. 18 is a waveform chart for explaining an operation of the conventional shift register circuit shown in FIG. 17. A description is given the operation of the conventional shift register circuit with reference to FIGS. 17 and 18.
First, the start signal ST becomes H level. Then, a clock signal CLK1 becomes H level. Thus, since the clock signal CLK1 at H level is supplied to the gate of the transistor NT101 of the first stage of shift register circuit 100a, the transistor NT101 is turned on. Thus, since the potential of the node ND101 is raised to H level, the signal at H level is supplied to the gate of the transistor NT102. Therefore, the transistor NT102 is turned on. Thus, since the potential of the node ND 102 is lowered to L level, the transistor NT103 is turned off. Thus, the potential of the node ND103 is raised to H level, so that the output signal SR1 at H level is output from the first stage of shift register circuit 100a. In addition, while the clock signal CLK1 is at H level, the potential at H level is charged to the capacitor C101.
Then, the clock signal CLK1 becomes L level. Thus, in the first stage of shift register circuit 100a, the transistor NT101 is turned off. Then, the start signal ST becomes L level. Here, even when the transistor NT101 is turned off, since the potential of the node ND101 is held at H level by the potential at H level stored in the capacitor C101, the transistor NT102 is held in on state. Therefore, since the potential of the node ND102 is not raised to H level, the output signal at L level is kept supplied to the gate of the transistor NT103. Thus, since the transistor NT103 is kept in off state, the output signal SR1 at H level is kept output from the first stage of shift register circuit 100a. 
Then, the clock signal CLK2 becomes H level. Thus, since the output signal SR1 at H level of the first stage of shift register circuit 100a is input to the second stage of shift register circuit 100b, the same operation as that of the first stage of shift register circuit 100a described above is performed. Therefore, the output signal SR2 at H level is output from the second stage of shift register circuit 100b. 
Then, the clock signal CLK1 becomes H level again. Thus, in the first stage of shift register circuit 100a, the transistor NT101 is turned on. At this time, the potential of the node ND101 is lowered to L level because the start signal ST becomes L level. Thus, since the signal at L level is supplied to the gate of the transistor NT102, the transistor NT102 is turned off. Therefore, since the potential of the node ND102 is raised to H level, the transistor NT103 is turned on. As a result, since the potential of the node ND103 is lowered from H level to L level, the output signal SR1 at L level is output from the first stage of shift register circuit 100a. According to the above-described operation, output signals (SR1, SR2, SR3 . . . ) at H level whose timings are shifted are sequentially output from respective stages of shift register circuits.
However, according to the conventional shift register circuit shown in FIG. 17, when the output signal SR1 at H level is output in the first stage of shift register circuit 100a, since the transistor NT102 is held in on state, there has been a problem that a through-current flows between VDD and VSS through the resistance R101 and the transistor NT102. In addition, when the output signal SR1 at L level is output, since the transistor NT103 is held in on state, there has been a problem that the through-current flows between VDD and VSS through the resistance R102 and the transistor NT103. Thus, there has been a problem that the through-current always flows between VDD and VSS. In addition, since the second and later stages of shift register circuits have the same constitution as that of the first stage of shift register circuit 100a, there has also been a problem that the through-current flows between VDD and VSS. Therefore, when the above conventional shift register circuit is used in a circuit for driving a gate line and a drain line of a liquid crystal display or an organic EL display, the power consumption in the liquid crystal display and the organic EL display is increased.